1. Field of the Invention
This invention relates generally to the art of microelectronic integrated circuits. More specifically, this invention relates to a method to monitor the state of erasure of a flash Electrically Erasable Programmable Read Only Memory (EEPROM) device during erase of the memory device. Even more specifically, this invention relates to a method to monitor the state of erasure of a flash Electrically Erasable Programmable Read Only Memory (EEPROM) device by monitoring the source voltage and by monitoring the rate of change of the source voltage during erase of the memory device.
2. Discussion of the Related Art
A microelectronic Electrically Erasable Programmable Read-Only Memory (Flash EEPROM) device includes an array of cells that can be independently programmed and read. The size of each cell and thereby the memory device are made small by omitting select transistors that would enable the cells to be erased independently. As a result all of the cells must be erased simultaneously as a block.
A memory of this type includes individual Metal-Oxide-Semiconductor (MOS) field effect transistor memory cells, each of which includes a source, drain, floating gate and control gate to which various voltages are applied to program the cell with a binary "1" or "0" or to erase all of the cells as a block.
The cells are connected in a rectangular array of rows and columns, with the control gates of the cells in a row being connected to a respective wordline and the drains of the cells in a column being connected to a respective bitline. The sources of the cells are connected together to a common source. This arrangement is known as a NOR memory configuration.
A cell is programmed by applying typically 9 volts to the control gate, 5 volts to the drain and grounding the source, which causes hot electrons to be injected from the drain depletion region into the floating gate. Upon removal of the programming voltages, the injected electrons are trapped in the floating gate and create a negative charge therein that increases the threshold voltage of the cell to a value in excess of approximately 4 volts.
The cell is read by applying typically 5 volts to the control gate, 1 volt to the bitline to which the drain is connected, grounding the source, and sensing the bitline current. If the cell is programmed and the threshold voltage is relatively high (.apprxeq.4 volts), the bitline current will be zero or at least relatively low. If the cell is not programmed or erased, the threshold voltage will be relatively low (.apprxeq.2 volts), the control gate voltage will enhance the channel, and the bitline current will be relatively high.
A cell can be erased in several ways. In one arrangement, applying typically 12 volts to the source, grounding the control gate and allowing the drain to float erases a cell. This causes the electrons that were injected into the floating gate during programming to be removed by Fowler-Nordheim tunneling from the floating gate through the thin tunnel oxide layer to the source. Alternatively, applying a negative voltage on the order of minus 10 volts to the control gate, applying 5 volts to the source and allowing the drain to float can erase a cell.
Another arrangement for erase is to use a constant current erase method. In the constant current erase method, a constant current is forced into the common source while applying a negative voltage on the order of minus 10 volts to the control gate and allowing the drain to float. The object of this arrangement is to provide a constant tunnel oxide field by maintaining a constant band-to-band tunneling current. During erase the source pulls up to a given voltage to maintain the required tunnel oxide field to sustain the constant band-to-band electric field. As electrons are removed from the floating gate of the cells by Fowler-Nordheim tunneling through the tunnel oxide, the vertical field across the tunnel oxide decreases and the source voltage will rise to a higher voltage to maintain the tunnel oxide field.
FIG. 2A illustrates a source pull-up power supply 200 that includes a constant current source 202. The constant current source 202 is connected to a voltage power supply V.sub.SS 204. A load line for the power supply 200 is illustrated in FIG. 2B, which plots source current I.sub.S as a function of source voltage V.sub.S. The current source 202 supplies a constant current of value I.sub.S MAX and limits the maximum voltage to V.sub.S MAX. The improvement provided by the constant current erase will be maintained as long as the source voltage V.sub.S is lower than V.sub.S MAX
FIG. 3 illustrates the effect of cycling in which the curve 300 represents the source pull up voltage in crease during the first erase cycle. The curve 302 represents the source pull up voltage characteristic at the end of several erase of cycles showing the effect of cycling. It will be noted that the curve 302 is above the curve 300, and that the source voltage V.sub.S can become clamped to the limit value V.sub.SS along the curve 302 long before the cells have become completely erased.
The cycling phenomenon is caused by the generation of hot electron-hole pairs resulting from band-to-band tunneling. Whereas Fowler-Nordheim tunneling from the floating gate through the tunnel oxide layer to the source results in erasure of a cell, band-to-band tunneling also occurs between the substrate and the source. When a positive voltage is applied to the source junction with the control gate negative, a deep depletion region is formed underneath the gate-to-source overlap region. The tunneling of valence band electrons into the conduction b and generates electron-hole pairs. The source junction collects the electrons and the holes are collected by the substrate.
Since the minority carriers (holes) generated thermally or by band-to-band tunneling in the source region flow to the substrate due to the lateral field near the Si-SiO.sub.2 interface, the deep depletion region remains present and the band-to-band tunneling can continue without creating an inversion layer. The generated holes gain energy because of the electric field in the depletion region. While the majority of these generated holes flow into the substrate, some of them gain sufficient energy to surmount the Si-SiO.sub.2 barrier and are trapped in the tunnel oxide layer. The trapped holes reduce the electric field that results in reduced band-to-band tunneling current. This effect causes the junction to "walkout" the source voltage and under constant current erase the source voltage increases to offset the reduction in the band-to-band electric field, which speeds up the erase (less number of erase pulses are required to complete the erase).
Therefore it is desirable to monitor the erase state of the memory in order to determine how far the erase operation has progressed and how many more erase pulses need to be applied.
As illustrated in FIG. 3, the main contribution to the source current V.sub.S is band-to-band tunneling (the Fowler-Nordheim tunneling current that causes the actual cell erasure is orders of magnitude lower), and this generally provides an accurate indication of the erase state. It is therefore possible to monitor the erase state of the memory by sensing the source voltage during erase. Also because the shape of the curves 300 and 302 are the same, it is also possible to monitor the erase state of the memory by sensing the rate of change of the source voltage during erase.
Therefore, what is needed is a method to monitor the state of erase by sensing the source voltage and/or the rate of change of the source voltage, wherein the method is independent of the effects of cycling.